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Implementing MIPS Processor with VHDL

Warning my lovely readers! The following will be a very technical article, but still, I can’t prevent your inner desire to keep reading this great article. 🙂

In my lab course on computer architecture, implementing processor in VHDL is one thing every electrical engineering student have to face. You know, it is like building your own Intel Core i7 yourself, but of course with much much much simplified processor architecture.

One of such thing is MIPS32, MIPS stands for Microprocessor without Interlocked Pipeline Stages. Cool huh?

MIPS is commonly be used for teaching processor architecture in not so great details. There are several stages every processor should have: Instruction Fetch, Instruction Decoding, Executing, Memory access, and write back. (are you confused? I’ve told you this will be very technical, it’s your fault. Keep reading!)

If you curious in the detail of the assignment, you should download the lab guide here ( unfortunately, it’s written in Indonesian only. No translation!

Instead of building our own hardware by connecting the individual physical logic gates, we’re implementing this MIPS processor in FPGA by writing VHDL code. Personally, I really enjoyed this lab course, I learned a lot when I was doing something. You know, I’m a kinesthetic learner. So I learn more and better when my hands grab something ‘real’.

As a bonus, here a screenshot of VHDL code I wrote days ago.

This is Arithmetic and Logical Unit component I wrote days ago. You really should not too hard reading the code above!

Have a nice weekend guys. 🙂

(cover image from

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